Part of the hierarchical development flow is about to get a lot simpler, thanks to a new standard being created by Accellera. What is less clear is how long will it take before users see any benefit.

Metastability is bound to occur in VLSI designs during clock domain crossing. For a robust and reliable design, metastability needs to be mitigated. To understand how to resolve it and how to build a ...

As chip designs grow in complexity and face tighter power constraints, depending on a single clock domain is no longer practical. Instead, most modern chips incorporate as many as dozens or even ...