CIOL

Synopsys DFT MAX mainstream use at 90nm and below

MOUNTAIN VIEW, USA: Synopsys Inc. announced that Synopsys' DFT MAX compression product has been successfully deployed at more than one hundred semiconductors companies from all industry segments to ...
EDN

Open-Silicon adopts Synopsys DFT MAX for ASICs

Synopsys has announced that Open-Silicon has adopted Synopsys' DFT MAX scan-compression technology to reduce the cost of testing its 130-, 90- and 65-nm ASIC designs while having minimal impact on ...
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Synopsys DFT MAX Compression Achieves Mainstream Usage at 90 Nanometers and Below

DFT MAX compression is much less intrusive on design flows and design performance than alternative solutions. Fragmented, bolt-on flows requiring separate design synthesis and scan compression ...
EDN

How DFT conquers chip complexity (continued)

Q: How important is DFT among semiconductor manufacturers? A: Given the complexity of chips being designed today, every semiconductor company knows how vital DFT is to ensuring product reliability.
CIOL

Open-Silicon adopts Synopsys' DFT MAX to lower ASIC costs

BANGALORE & CALIFORNIA, US: Synopsys, Inc., a leader in semiconductor design software, recently announced that Open-Silicon, a leading supplier of predictable, reliable and cost-effective ASIC ...
Finanznachrichten

Oki Adopts DFT MAX to Improve Test Quality

DFT MAX implements compression on-chip that results in significantly less data required for each test pattern. Using DFT MAX, Oki was able to apply comprehensive at-speed testing in addition to its ...
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Synopsys DFT MAX Cuts Test Costs on Nanometer Designs

The DFT MAX solution reduces costs associated with test data inflation by performing on-chip compression to reduce by 10-50 times the volume of information to be stored in tester memory. DFT MAX ...