Hackaday

FPGA Used VHDL For Fractals

Over on GitHub, [ttsiodras] wanted to learn VHDL. So he started with an algorithm to do Mandelbrot sets and moved it to an FPGA. Because of the speed, he was able to accomplish real-time zooming. You ...

MicroCloud Hologram Inc. Launches FPGA-Based High-Performance Surface Code Quantum Simulation Platform

MicroCloud Hologram Inc. (NASDAQ: HOLO), (“HOLO” or the "Company"), a technology service provider, launched a simulator that fully leverages the unique advantages of FPGA (Field-Programmable Gate ...
TechRepublic

Simulation and Optimization of VHDL Code for FPGA-Based Design Using Simulink

Simulations and prototyping have been a very important part of the electronics industry since a very long time. In recent years, FPGA’s have become increasingly important and have found their way into ...
Design-Reuse

Powerful FPGA Design Creation and Simulation IDE Adds VHDL-2019 Support & OSVVM Enhancements

Aldec’s Active-HDL™ enables FPGA designers to take full advantage of the many features within the latest revision to VHDL and helps improve design verification efficiency. Henderson, NV – January 20, ...
Hackaday

Did You Know YoSys Knows VHDL Too?

We’ve been fans of the Yosys / Nextpnr open-source FPGA toolchain for a long while now, and like [Michael] we had no idea that their oss-cad-suite installer sets up everything so that you can write in ...
Seeking Alpha

MicroCloud Hologram Inc. FPGA-Based High-Performance Surface Code Quantum Simulation Platform: Efficient Error Correction Algorithm Validation under Rotated Layout

SHENZHEN, China, Feb. 25, 2026 /PRNewswire/ -- MicroCloud Hologram Inc. (HOLO), ("HOLO" or the "Company"), a technology service provider, has developed a surface code quantum simulator based on FPGA.
Semiconductor Engineering

FPGA VHDL Verification

This is actually possible – and with an average efficiency improvement of 20% to 50% for medium to high complexity FPGAs. Less for data path oriented designs and more for control or protocol oriented ...
Yahoo Finance

Verific's SystemVerilog, VHDL Parsers Chosen by Flexras Technologies to Serve as Front End for FPGA-Based Prototyping Tool

ALAMEDA, CA--(Marketwired - Aug 5, 2014) - Verific Design Automation today announced Flexras Technologies, provider of high-performance partitioning software, has implemented its industry-standard, ...
EDN

Product how-to: Achieving STARC and DO-254 compliance using HDL Coder-generated code

HDL Coder generates target independent, synthesizable Verilog and VHDL code from MATLAB functions, Simulink models, and Stateflow charts. The generated HDL code is bit-true and cycle-accurate to ...
TechRepublic

Design of FPGA Based 32-Bit Floating Point Arithmetic Unit and Verification of Its VHDL Code Using MATLAB

Most of the algorithms implemented in FPGAs used to be fixed-point. Floating-point operations are useful for computations involving large dynamic range, but they require significantly more resources ...